GNU Make

GNU Make processes a Makefile, a text file that provides instructions for building the software project. It iterates through the instructions and determines the rules specified and the target output to generate.

A Makefile rule is a named group of commands that work together to create output file(s) called a target—usually a library or executable. If the target already exists and the source hasn’t been updated, make is smart enough to skip unnecessary build steps to reduce compile time.

Make was initially developed by Stuart Feldman in April of 1976, but GNU released its free software version of the tool in the late 1980s. Version 3.56 is still available (via diffs) from the GNU FTP server, dating back to September 23, 1989.

The latest version is 4.3, released January 19, 2020.

Makefiles are the primary way you instruct GNU Make to build your software project. Let’s examine a simple Makefile.

# Define our compiler as GCC

CC=gcc

# The main rule and targets

hello: hello.c hellolib.c

$(CC) -o hello hello.c hellolib.c

# A rule to clean binaries

clean:

rm -f hello

In this simple project, we first define a variable called CC. While not necessary, this lets us specify the compiler to use for the entire project. If we wanted to change it later, we would only have to alter one line. Make allows you to define as many variables as you wish and use them in your rules, reducing typing and refactoring effort.

The first rule in the file, named “hello”, becomes the default rule and is processed when you run the “make” command. The files involved are listed so make can optimize their build order and selection, and the following line, preceded by a TAB, lists the command(s) to run to create the target. Note the use of the previously defined variable CC.

Finally, we define a clean rule, invoked via the “make clean” command, which removes the binary generated to perform a clean build when necessary. The clean rule is not required but is handy to have, especially if you generate multiple binaries.

You could add to this example by including an install rule. Many instructions for common software packages tell you to run “make install”. Doing so simply triggers the install rule, which commonly includes commands that copy the compiled binaries to their necessary locations.

Many newcomers to GNU Make encounter syntax issues with their Makefiles. It is important to indent your build commands in a rule with a single tab. Spaces will not work and cause make to execute your Makefile incorrectly.

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